Design and implementation of low power superscalar processor
The processor architecture designed here is a modest step forward towards the designing of a power optimized superscalar processor. The heavy popularity of data intensive applications nowadays is demanding for high performance hardware but at a very strict power budget. This poses a possible chance of stagnation in the field of processor design. Therefore, the design and implementation of a superscalar processor can throw some light on the ways to curb the occurrence of such a possibility. The processor architecture designed and implemented is a 2-issue superscalar incorporating Branch prediction, Register renaming and Tomasulo algorithm. The execute and memory tasks are combined into a single stage. The write back and retire tasks are carried out in another single stage. So, the processor is made up of 6 stages : Fetch, Decode, Rename, Dispatch, Execute Memory, Write Back Retire. The instruction set architecture used is derived from ARM instruction set and the assembly commands are a subset of the ARM assembly instruction set.
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