Design and implementation power interrupt-driven processor using RISC-V ISA
From the past mistakes of popular ISA's and with the motivation to work on one of the most important abstraction layer, the RISC-V ISA steps forth to upend the status quo. Working towards a low power processor that entertains interrupts occurring at regular and irregular intervals, provides a real insight into the handling of the interrupts. And the simplicity of RISC-V adds to its sophistication. Low power synthesis, by its very nature, deals with the design implementation of an abstract circuit behavior using the constraints and the libraries provided to it. The constraints, specifically provide the set of rules, limitations and the designer's intent towards the desired low power behavior. This desired behavior usually comes at the cost of some other design parameters, sort of a trade-off between area, delay and increased circuit complexity. But even if we set aside the environmental concerns associated with the power consumption of electronic devices, there are multiple other reasons like cost, reliability and robustness that favor this trade-off.
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