Search
Now showing items 21-30 of 56
Built-in self test architecture for mixed signal systems
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and ...
Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the ...
CMOS RFIC mixer design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
A CMOS RF (Radio Frequency) up/down conversion mixer results in a reasonable increase in transceiver integration and a reduction in cost. The design of mixers faces many compromises between conversion gain(GC), local ...
Design & layout of a low voltage folding & interpolation ADC for high speed applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) plays a vital role
in mixed analog signalling, communication and digital signal processing world. Now a day,
the demand for designing of high ...
D-latch based low power memory design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2015)
Low power consumption is the main attraction of the digital circuit design in the
Sub threshold region of operation. In this region of operation less energy is
consumed for active operation and less leakage power is ...
CTS and CCOpt metodology's to achieve low skew-low power clock.
(Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
In synchronous VLSI chips, clock distribution network plays an important role. The quality of clock network mainly effects the performance of the chip, because the speed of data transfer depends on clock signal. Achieving ...
Design and layout of single bit per stage pipelined ADC
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
The concept of pipe-lining, often used in digital circuits, can also be applied in the analog domain. It helps to achieve higher speed where several operations must be performed serially. In this work, pipe-lining is ...
Design and synthesis of asynchronous circuits
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
For a very long time, there has been a requirement of circuits that can overcome the difficulties caused by the delay assumptions involved in a physical system. With decreasing on-chip dimensions of circuits as a result ...
Design of a novel high linearity down conversion mixer for GSM band applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Double balanced Gilbert cell mixer (GCM) is the mostly used kind of mixer as it provides
conversion gain and has port to port isolation. This mixer lacks in linearity and noise figure
which are to be taken care in designing ...
Design of low voltage high performance, wide bandwidth current feedback amplifier with complementary input pair
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
This thesis presents the work done on the design of a low voltage high performance, wide bandwidth current feedback amplifier [CFA] with complementary input pair. The design is carried out in 1.8 V, 0.18 micron CMOS process. ...