Analysis of various DFT techniques in the ASIC designs

Abstract

With the increasing demand of mobile communication industry and highly progressive VLSI technology, muti-million gates silicon chips are in the market. And to have fault free, reliable chips, extended facility of testable circuit has to be added into the original design. The design technique which includes the testability logic into the design at the logical synthesis level is known as Design for Test abbreviated as DFT [1].

To achieve better fault coverage, I have chosen full scan chain insertion technique for OR1200 design. OR1200 is a 32-bit microprocessor with 5-stage pipeline [12]. Its RTL code is taken from opencores.org and Cadence RTL Compiler version 11.1 is used for logic synthesis. For testing and verification, Encounter Test Version 11.1 and NCVerilog simulator is used.

To improve the testability of the design, Deterministic fault analysis and Random Resistant Fault Analysis techniques are also added to the design. Effects of all hardware DFT techniques are analysed in terms of area, dynamic power dissipation and gate count.

Main low power technique i.e. clock gating is also inserted along with DFT to achieve better performance in terms of power dissipation. DFT causes 25% of increase in die area and 12% of increase in dynamic power. This is acceptable as we will get OR1200 design with 99.67% fault coverage area.