Please use this identifier to cite or link to this item: http://drsr.daiict.ac.in//handle/123456789/431
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dc.contributor.advisorDubey, Rahul
dc.contributor.authorVansadiya, Mayursinh K.
dc.date.accessioned2017-06-10T14:40:31Z
dc.date.available2017-06-10T14:40:31Z
dc.date.issued2013
dc.identifier.citationVansadiya, Mayursinh K. (2013). Development of verification environment for multiply-accumulate unit using system verilog. Dhirubhai Ambani Institute of Information and Communication Technology, x, 64 p. (Acc.No: T00394)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/431
dc.description.abstractNowadays, Application Specific Integrated Circuit (ASIC) design are becoming complex, even designs based of Field Programmable Gate Array (FPGA) are also complex. So it is very difficult to verify the design through waveform or log files. For that, some self-checking environment is needed to verify the functionality of the design. In my thesis work, I have worked upon developing the verification environment using System Verilog. In signal processing, most of the transformation uses multiply and addition function frequently. So Multiply-Accumulate (MAC) is the dedicated hardware to improve the speed of Digital Signal Processor (DSP). In this thesis, I have written a Verilog HDL code for MAC unit of DSP in ModelSim SE 6.3f and synthesized in Xilinx ISE 8.1i. System Verilog is used to verify MAC unit. Simulations are done using tool named ModelSim SE 6.3f of Mentor Graphics®. The constrained-randomised inputs and direct inputs are fed to the Design Under Test (DUT) as well as reference model. The output from both systems are compared to check functionality. The functional coverage and code coverage are measured for correctness of the design. The constrained random vectors and direct test cases are used to achieve higher coverage.
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.subjectMultiply-Accumulate Unit
dc.subjectDevelopment and Verification
dc.subjectMultiply-Accumulate Unit
dc.subjectSystem Verilog
dc.subjectElectrical and Electronic Engineering
dc.subjectApplication Specific Integrated Circuit
dc.classification.ddc621.3815 VAN
dc.titleDevelopment of verification environment for multiply-accumulate unit using system verilog
dc.typeDissertation
dc.degreeM. Tech
dc.student.id201111016
dc.accession.numberT00394
Appears in Collections:M Tech Dissertations

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