Browsing by Author "Zaveri, Mazad S"

Now showing items 1-9 of 9

    • 16 bit dual threshold voltage conditional carry adder. 

      Dobaria, Renish (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      So many different circuits and different schemes are applied to make circuit faster and less power consumptive. In this thesis, 16-bit dual threshold voltage conditional carry adder, with two proposed modification for ...

    • CMOS current-based mixed-signal architecture for vector-matrix multiplication 

      Chhaya, Vaibhav (Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
      In present days electronic devices become faster. Computations like vector matrix multiplication become more and more compliant and lengthy. For that CMOS based vectormatrix multiplication architecture, with external ...

    • FPGA based platform for spiking neural network 

      Chavada, Sujit (Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
      Neuromorphic engineers are studying the nervous system and trying to emulate its function and organization in their computational and robotics systems. They are hoping to match the human brain in vision, hearing, pattern ...

    • FPGA implementation of environment/noise classification using neural networks 

      Ambasana, Nikita B. (Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
      The purpose of this thesis is to give an insight into the implementation of a system of neural networks, for the tasks of Noise/Environment Modeling, Feature Extraction and Classification of Noise/Environment, on a Field ...

    • HDL based implementation of a node of hierarchical temporal memory. 

      Vyas, Pavan R. (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      The main intention of this thesis is to give the basic information about the implementation of a node of one of the neural network algorithms. The main purpose of this thesis is to design, implement and analyze the node ...

    • HDL implementation of a node of bayesian polytree interface 

      Patel, Jayendra (Dhirubhai Ambani Institute of Information and Communication Technology, 2014)
      In this thesis, we have particularly focussed on the aspects of the hardware implementation of the Bayesian inference framework within the George and Hawkins’ model. This framework is based on Judea Pearl’s belief propagation. ...

    • HDL implementation of associative memory based instruction predictor for power reduction 

      Rangani, Jaydeep (Dhirubhai Ambani Institute of Information and Communication Technology, 2014)
      Now a days, power consumption in digital integrated circuits/systems is a major issue. The goal here is to reduce power consumption, by assuming the circuit is divided in different power consuming modules, observing their ...

    • HDL implementation of palm associative memory 

      Kacheria, Rachit M. (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      The objective of this paper is to implement and analyze the palm associative memory proposed by G. Palm [1]. In this paper, a design implementation of this algorithm, based on Verilog HDL (hardware description language) ...

    • Study of power in CR-SRAM in context of precharge reference voltage. 

      Rupapara, Kripal D. (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      In Morden times power dissipation in electronic circuits has become more important due to increase use of portable and handheld devices. Increased operating frequency results in more power consumption in almost every VLSI ...