Now showing items 1-6 of 6

    • 1v rail to tail operational amplifier design for sample and hold circuits 

      Kumar, Mahesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      At low voltage, the input common mode voltage of Operational amplifier is limited which restricts its use as a buffer. This works deals with designing a rail to rail amplifier. The Thesis presents a 1V rail to rail operational ...
    • Column decoder for memory redundant cell array 

      Nahar, Pinky (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      As the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy ...
    • Design issues in direct conversion receiver 

      Gupta, Amit Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      The wireless system is being rapidly proliferated in our life. The growing of capacity in wireless communication requires a new type of wireless communication method which does not affect current work on circuits and systems ...
    • Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors 

      Sesha Sai, Aduru Venkata Raghava (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor ...
    • Design of the high speed, high accuracy and low power current comparators 

      Chasta, Neeraj Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”. A current ...
    • Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier 

      Ranjith, P (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      This thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. ...