1.5V, 2.4GHz highly linear CMOS downconversion mixer
In the tremendous growth of wireless handheld devices, low power consumption becomes a major consideration in radio frequency integrated circuit (RFIC) designs. This thesis explores low voltage low power RFIC design for CMOS mixer through their applications in a RF front-end transceiver.A highly linear CMOS down-conversion mixer is designed to operate at 1.5V for single battery solution. Mixer perform frequency down-conversion from a 2.4GHz radio frequency (RF) input signal to a 100MHz intermediate frequency (IF) output signal. The mixer circuit has been simulated in TSMC 0.18μm CMOS technology. Low voltage operation is achieved by using a folded cascode topology. The mixer uses a wide range constant gm cell at input RF stage to increase the linearity (IIP3) performance. The proposed mixer has 0.92dB conversion gain, 17.7dB noise figure, 3.08 1 dB compression point (P-1 dB), 13.8dBm third-order input intercept point (IIP3) and consumes 8.1mW DC power at 1.5V supply voltage. The design ensures that all the transistors remain in saturation, and mixer does perform satisfactorily for +/-50mV variation of the threshold voltage from the nominal value for both NMOS and PMOS transistors. The mixer is simulated for +/- 50mV threshold voltage variations for both NMOS and PMOS transistors. Temperature effects on this circuit were also investigated.
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