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dc.contributor.advisorMandal, Sushanta
dc.contributor.advisorNagchoudhuri, Dipankar
dc.contributor.authorJain, Mahavir Rajmal
dc.date.accessioned2017-06-10T14:37:57Z
dc.date.available2017-06-10T14:37:57Z
dc.date.issued2009
dc.identifier.citationJain, Mahavir Rajmal (2009). Built-in self test architecture for mixed signal systems. Dhirubhai Ambani Institute of Information and Communication Technology, xii, 50 p. (Acc.No: T00219)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/256
dc.description.abstractBuilt-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and used for digital circuitry due to well defied fault models and advanced designs tools and techniques available. But with more analog circuitry being built on same platform with digital circuitry, the necessity for BIST architecture of mixed signal system on chip is increasing. The proposed BIST scheme is developed to test the data converters, both DAC and ADC on chip as well as other analog IP modules depending on specification of design without/least affecting the architecture of actual design and without making use of any complex DSP circuitry. The concept of internet node access based testing of digital blocks is also used for dynamic parameter of DAC like offset voltage and gain error, monotonicity and linearity non-specific BIST scheme. Letter the digital control logic protion of SAR ADC is tested with scan-chain insertion and thus overall functionality of SRA ADC is verified. A simple comparison based method is also proposed for other type ADCs. For other anlog IPs, we propose IP-based testing where digital to analog converted test signals can be applied depending on specifications of IP design from vendor without affecting architecture of the design. The output from IPs are taken at different nodes and applied directly to ADC on chip. The digitized output response is then compared with expected response to test the functionality of the DUT and find out its deviation from desired value to achieve pre-defined level of accuracy. The design failing any of the sequence of afore-mentioned test is discarded faulty. The circuitry is designed and evaluated at schematic level using TSMC complementary metal oxide-semiconductor (CMOS) 0.5um technology.
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.subjectAutomatic test equipment
dc.subjectIntegrated circuits
dc.subjectVerification
dc.subjectIntegrated circuits
dc.subjectDesign and construction
dc.subjectSignal processing
dc.subjectDigital techniques
dc.subjectMixed signal circuits
dc.subjectTesting
dc.subjectMixed signal circuits
dc.subjectDesign and construction
dc.subjectMetal oxide semiconductors
dc.subjectDesign and construction
dc.subjectIntegrated circuits
dc.subjectVery large scale integration
dc.subjectlectronic circuit design
dc.subjectSignal generators
dc.subjectDesign and construction
dc.classification.ddc621.381548 JAI
dc.titleBuilt-in self test architecture for mixed signal systems
dc.typeDissertation
dc.degreeM. Tech
dc.student.id200711031
dc.accession.numberT00219


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