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CMOS latched comparator design for analog to digital converters
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save ...
Area reduction in 8 bit binary DAC using current multiplication
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
A proposed current multiplication technique is applied on 8 bit binary current steering Digital-to -Analog Converters with LSB 150 μA, to reduce area. MSB 1 and MSB 2 current are first kept half to reduce area and then ...
Fault diagnosis algorithm for a flash ADC using oscillation based testing technique
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising ...