Search
Now showing items 1-7 of 7
Low power microprocessor design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
This research work tries to reduce the power consumption of a processor with signal processing features. For low power design, focus is on developing ‘Low power synthesizable Register File’, as the initial study shows that ...
1v rail to tail operational amplifier design for sample and hold circuits
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
At low voltage, the input common mode voltage of Operational amplifier is limited which restricts its use as a buffer. This works deals with designing a rail to rail amplifier. The Thesis presents a 1V rail to rail operational ...
Investigation of low power design of left-right leap frog array multiplier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
This thesis addresses the Low Power design of 12 bit LRLFAM at the Layout, circuit and logic levels. A new Low power Booth-Recoder (BR), and Multiplexer based partial product generated are designed using pass-Transistor ...
Design methodology for architecting application specific instruction set processor
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
Application Specific Instruction-set Processors (ASIP), also referred as extensible processors, represent the state-of-the-art microprocessor architecture. ASIPs are practically leading towards the realization of ...
Design of low voltage high performance, wide bandwidth current feedback amplifier with complementary input pair
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
This thesis presents the work done on the design of a low voltage high performance, wide bandwidth current feedback amplifier [CFA] with complementary input pair. The design is carried out in 1.8 V, 0.18 micron CMOS process. ...
Low drop-out (LDO) voltage regulator without off-chip capacitor
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Designing of Low Drop-Out Voltage Regulators (LDOs) operating without a large off-chip capacitor, having a very good transient response and maintaining the loop stability for full load current range in low supply voltage ...
Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
This thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. ...