Hardware-software design of real-time MPEG-2 video encoder
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The goal of this thesis is to analyze how MPEG-2 encoder can be optimized for real-time streaming applications Hw/Sw design re-configurable platform is chosen, where part of algorithm runs on CPU or on re-programmable hardware as a hardware accelerator. The structures is based on block level pipelining(BLP) where each frame is divided in 8X8 pixel blocks and each block is processed through the MPEG-2 video compression algorithm designed in a pipeline fashion and optimized so at to achieve maximum throughput. Here, we have designed an encoder for a Xilinx Zynq7000 series SoPC FPGA platform named as Zedboard. Initially, the encoder is designed in C and run on ARM cortex A-9 processor. This code is then profiled for ARM processor based on computational requirements. The results are analyzed and the computationally intensive subsystems are implemented as hardware accelerators to attain the desired features.
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