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Now showing items 11-20 of 34
Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the ...
Design & layout of a low voltage folding & interpolation ADC for high speed applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) plays a vital role
in mixed analog signalling, communication and digital signal processing world. Now a day,
the demand for designing of high ...
CTS and CCOpt metodology's to achieve low skew-low power clock.
(Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
In synchronous VLSI chips, clock distribution network plays an important role. The quality of clock network mainly effects the performance of the chip, because the speed of data transfer depends on clock signal. Achieving ...
Design of a CMOS variable gain amplifier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new ...
Design of the high speed, high accuracy and low power current comparators
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”.
A current ...
Design of voltage reference circuits
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
Shrinking device dimensions in advancing CMOS technologies require lower supply voltages to ensure device reliability. As a result, analog circuit designers are faced with many challenges in finding new ways to build analog ...
High speed sample and hold circuit design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ...
Low power SRAM design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power ...
Low power BIST architecture for fast multiplier embedded core
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
A typical core is deeply embedded in the chip of a system so that direct access to its input/output is not possible. Built in self test (BIST) structures are excellent solutions for testing embedded cores.
In this work, ...
Novel 7T SRAM cell design for low power cache applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Scaling in integrated circuit technology directly paves way to increased package density,
thereby increasing onchip power. With continuous scaling, low power design techniques
results in efficient use of silicon die. ...