Browsing by Subject "Digital-to-analog converters"

Now showing items 1-5 of 5

    • 10-bit high speed high SFDR current steering DAC 

      Bapodra, Dhairya B. (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      The Thesis presents an attempt to design a 10-bit High Speed High SFDR Current Steering DAC with a simple and different approach. Most of earlier approaches contain complex design and bulky unary portion. Here an approach ...

    • Area reduction in 8 bit binary DAC using current multiplication 

      Upraity, Maitry (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      A proposed current multiplication technique is applied on 8 bit binary current steering Digital-to -Analog Converters with LSB 150 μA, to reduce area. MSB 1 and MSB 2 current are first kept half to reduce area and then ...

    • CMOS latched comparator design for analog to digital converters 

      Gupta, Amit Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save ...

    • Fault diagnosis algorithm for a flash ADC using oscillation based testing technique 

      Aggarwal, Divya (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising ...

    • Self-calibrating technique for digital-to-analog converter in successive approximation register analog-to-digital converter 

      Patel, Sujit Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      Successive Approximation Register (SAR) analog to digital converter resolution is limited mainly by the capacitor ratio error; comparator offset voltage and capacitor voltage dependence error. A SAR ADC resolution is limited ...