Browsing M Tech Dissertations by Title

Now showing items 457-476 of 820

    • Low complexity 2-level (FFT-GOERTZEL) spectrum sensing method for cognitive radio 

      Bhatt, Prakruti Vinodchandra (Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
      Energy detection in frequency domain is a preferred technique for the spectrum sensing and the accuracy of frequency estimation depends on the Discrete Fourier Transform (DFT) size. Instead of computing full length (N) ...

    • Low cost design of IFFT module for dolby AC-3 decoder 

      Gupta, Akshay Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      Dolby AC-3 is a flexible audio data compression technology capable of encoding a range of audio channel formats into a low rate bit stream. AC-3 is the de facto audio standard for high-end digital consumer multimedia ...

    • Low drop-out (LDO) voltage regulator without off-chip capacitor 

      Agarwal, Gopal (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      Designing of Low Drop-Out Voltage Regulators (LDOs) operating without a large off-chip capacitor, having a very good transient response and maintaining the loop stability for full load current range in low supply voltage ...

    • Low noise amplifier design at 2 GHz 

      Mavani, Kausha (Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
      Low Noise Amplifier (LNA) is one of the most important building blocks of any wireless receiver. In this an attempt has been made to study two types of LNA designs. The first design is the conventional which consists of ...

    • Low power and high speed sample and hold circuit 

      Trivedi, Ronak (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      In this thesis work the design of a high speed and low power CMOS sample and hold circuit as a front-end block of pipelined analog-to-digital converter is described. The circuit consists of bottom-plate sampling with ...

    • Low power ASIC design using CPF 

      Patel, Darshal (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      In recent years, with remarkable growth in personal computing devices, consumer electronics and communication devices, there has been seen urgent requirement for high speed computation and increased functionality. The ...

    • Low Power ASIC Implementation of SC-FDMA 

      Tandel, Deep (Dhirubhai Ambani Institute of Information and Communication Technology, 2017)
      "Single Carrier-Frequency Division Multiple Access (SC-FDMA), a modified version of Orthogonal Frequency Division Multiple Access (OFDMA) is the preferred uplink access scheme for Long Term Evolution (LTE). We aim to design ...

    • Low power BIST architecture for fast multiplier embedded core 

      Vij, Aditya (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      A typical core is deeply embedded in the chip of a system so that direct access to its input/output is not possible. Built in self test (BIST) structures are excellent solutions for testing embedded cores. In this work, ...

    • Low power high slew-rate adaptive biasing circuit for CMOS amplifiers 

      Rao, A. Narayana (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      Adaptive biasing technique in analog and mixed signal integrated circuit design is used mainly to reduce the power and improve the driving capability. It has found many applications, like power amplifiers in RF communication ...

    • Low power high speed amplifier design 

      Bensal, Jitendra Babu (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      The operational amplifier (op-amp) is one of the important component in analog to digital converters. The power consumption of these converters mostly depend on the op-amps used. The accuracy and speed performance of analog ...

    • Low power improved full scan BIST 

      Parashar, Umesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      Low power testing of VLSI circuits has recently become an area of concern due to yield and reliability problems. Past research on low power testing has shown that, switching activity and test time are the main factors that ...

    • Low power microprocessor design 

      Bhatt, Vishal (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      This research work tries to reduce the power consumption of a processor with signal processing features. For low power design, focus is on developing ‘Low power synthesizable Register File’, as the initial study shows that ...

    • Low power SAR ADC with split capacitor DAC 

      Dhalvaniya, Pankaj (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      Analog to Digital convertor and Digital to Analog convertors plays a vital role in Mixed Signal Design. Nowadays, the demand for designing of Low power, Moderate Resolution ADCs are increasing for Bio-medical applications ...

    • Low power SRAM design 

      Bambhaniya, Prashant (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power ...

    • Low-power multi-ported register file for digital signal processors 

      Aguduri, Nagamanoj Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
      Digital Signal Processors (DSPs) also come under the category of processors in which Multi-ported register files can find their applications widely. Most of the DSP applications do not benefit from further speeding-up after ...

    • Low-power pipelined crypto-core using a backup flip-flop 

      Patel, Sagar (Dhirubhai Ambani Institute of Information and Communication Technology, 2015)
      With increasing clock frequencies, power-aware computing has become a critical concern in the VLSI design. One of the most effective and widely used method for lowering the power is DVS (Dynamic Voltage Scaling), which ...

    • Low-rank and sparse decomposition of compressively-sensed matrices: applications to surveillance video processing 

      Lekshmi, Ramesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2015)
      Detection, recognition and tracking are three of the primary tasks involved in surveillance video processing. Given the huge amount of data generated by surveillance systems, it is desirable to use compressed sensing ...

    • Machine learning in financial data EPS estimates 

      Sharma, Rohan (2020)
      The project “EPS Estimates” is as the name suggests a work on Earnings Per Share figures released by companies annually and quarterly. The whole project is intended to come up with a better consensus methodology for EPS ...

    • Manifold valued image segmentation 

      Bansal, Sumukh (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      Image segmentation is the process of partitioning a image into different regions or groups based on some characteristics like color, texture, motion or shape etc. Segmentation is an intermediate process for a large number ...

    • MBE: Client Side Secure Data Deduplication Based on Merkel Tree 

      Joshi, Kriti (2021)
      Several secure data deduplication protocols are recently proposed to maintain unique data copies at the cloud service providers (CSP’s) and utilize the storage space efficiently. Though many Message Locked Encryption (MLE) ...