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Now showing items 11-20 of 25
Design of a CMOS variable gain amplifier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new ...
Design of a high speed I/O buffer
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. ...
Design of row decoder for redundant memory cell (SRAM)
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory ...
Design of the high speed, high accuracy and low power current comparators
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”.
A current ...
Design of voltage reference circuits
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
Shrinking device dimensions in advancing CMOS technologies require lower supply voltages to ensure device reliability. As a result, analog circuit designers are faced with many challenges in finding new ways to build analog ...
Fault diagnosis algorithm for a flash ADC using oscillation based testing technique
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising ...
High speed sample and hold circuit design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ...
Low noise amplifier design at 2 GHz
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
Low Noise Amplifier (LNA) is one of the most important building blocks of any wireless
receiver. In this an attempt has been made to study two types of LNA designs. The first
design is the conventional which consists of ...
Low power SRAM design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power ...
Self-calibrating technique for digital-to-analog converter in successive approximation register analog-to-digital converter
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Successive Approximation Register (SAR) analog to digital converter resolution is limited mainly by the capacitor ratio error; comparator offset voltage and capacitor voltage dependence error. A SAR ADC resolution is limited ...