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Now showing items 11-20 of 27
Design of multi-standard RF front end receiver using novel low IF topology
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
This thesis presents the multi-standard receiver architecture and the corresponding RF front-end design supporting Bluetooth and IEEE 802.11a WLAN standards. To maximize the level of component share in the proposed ...
Design methodology for architecting application specific instruction set processor
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
Application Specific Instruction-set Processors (ASIP), also referred as extensible processors, represent the state-of-the-art microprocessor architecture. ASIPs are practically leading towards the realization of ...
Area reduction in 8 bit binary DAC using current multiplication
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
A proposed current multiplication technique is applied on 8 bit binary current steering Digital-to -Analog Converters with LSB 150 μA, to reduce area. MSB 1 and MSB 2 current are first kept half to reduce area and then ...
Built-in self test architecture for mixed signal systems
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and ...
CMOS RFIC mixer design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
A CMOS RF (Radio Frequency) up/down conversion mixer results in a reasonable increase in transceiver integration and a reduction in cost. The design of mixers faces many compromises between conversion gain(GC), local ...
Design and synthesis of asynchronous circuits
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
For a very long time, there has been a requirement of circuits that can overcome the difficulties caused by the delay assumptions involved in a physical system. With decreasing on-chip dimensions of circuits as a result ...
Design of low voltage high performance, wide bandwidth current feedback amplifier with complementary input pair
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
This thesis presents the work done on the design of a low voltage high performance, wide bandwidth current feedback amplifier [CFA] with complementary input pair. The design is carried out in 1.8 V, 0.18 micron CMOS process. ...
Fault diagnosis algorithm for a flash ADC using oscillation based testing technique
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising ...
Low drop-out (LDO) voltage regulator without off-chip capacitor
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Designing of Low Drop-Out Voltage Regulators (LDOs) operating without a large off-chip capacitor, having a very good transient response and maintaining the loop stability for full load current range in low supply voltage ...
Low power improved full scan BIST
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
Low power testing of VLSI circuits has recently become an area of concern due to yield and reliability problems. Past research on low power testing has shown that, switching activity and test time are the main factors that ...