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Now showing items 31-40 of 54
Design of row decoder for redundant memory cell (SRAM)
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory ...
Design of the high speed, high accuracy and low power current comparators
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”.
A current ...
Fault diagnosis algorithm for a flash ADC using oscillation based testing technique
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising ...
High speed, low offset voltage cmos comparator
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is ...
Low drop-out (LDO) voltage regulator without off-chip capacitor
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Designing of Low Drop-Out Voltage Regulators (LDOs) operating without a large off-chip capacitor, having a very good transient response and maintaining the loop stability for full load current range in low supply voltage ...
Low power improved full scan BIST
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
Low power testing of VLSI circuits has recently become an area of concern due to yield and reliability problems. Past research on low power testing has shown that, switching activity and test time are the main factors that ...
Novel 7T SRAM cell design for low power cache applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Scaling in integrated circuit technology directly paves way to increased package density,
thereby increasing onchip power. With continuous scaling, low power design techniques
results in efficient use of silicon die. ...
Path planning of data mule using responsible short circuit with steiner points
(Dhirubhai Ambani Institute of Information and Communication Technology, 2015)
We have studied the problem of data aggregation method in wireless sensor network
using the data mule. In data mule approach, Data mule is the mobile entity
which can collect the data from stationary sensor node in the ...
Reduction of power using innovative Clock Gating and Multi Vth techniques in digital design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Low power is one of the most important issues in today’s ASIC (Application Specific
Integrated Circuit) design. As the transistors scale down, power density becomes high and
there is immediate need of reduction in power. ...
Robust surface coverage using deterministic grid based deployment in wireless sensor networks
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
The rapid progress in the field of wireless communication ans MEMS technology has made wireless sensor networks (WSN) possible. These networks may have low cost sensors deployed which are capable of sensing any activity ...