Browsing by Author "Bhatt, Amit"

Now showing items 1-20 of 40

    • Adaptive caches: a smart way to reduce leakage power dissipation in cache memories 

      Jampani, Sharmila (Dhirubhai Ambani Institute of Information and Communication Technology, 2014)
      The advancement of circuit minimization in CMOS echnology has not only led to extraordinary improvements in microprocessor performance but has also caused the density of energy dissipation in a chip to increase. This ...

    • Analysis of various DFT techniques in the ASIC designs 

      Rathod, Gayatri Manohar (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      With the increasing demand of mobile communication industry and highly progressive VLSI technology, muti-million gates silicon chips are in the market. And to have fault free, reliable chips, extended facility of testable ...

    • ASIC Implementation of STBC MIMO-OFDM System 

      Pratik, Harshit (Dhirubhai Ambani Institute of Information and Communication Technology, 2017)
      "Space-Time Block Coded Multiple-Input Multiple-Output (STBC MIMO) System in combination with Orthogonal Frequency Division Multiplexing (OFDM) System is one of the currently used wireless technology around the world. MIMO ...

    • Comparative Study: Neural Networks on MCUs at the Edge 

      Anand, Harshita (2021)
      Computer vision has evolved excessively over the years, the sizes of the processor and camera shrinking, rising the computational complexity and power and also becoming affordable, making it achievable to be integrated ...

    • CTS and CCOpt metodology's to achieve low skew-low power clock. 

      Sreekanth, M. (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      In synchronous VLSI chips, clock distribution network plays an important role. The quality of clock network mainly effects the performance of the chip, because the speed of data transfer depends on clock signal. Achieving ...

    • Design and Implementation of 3-stage Low Power Interrupt Driven Processor using RISC-V ISA 

      Kosta, Ankur (2020)
      The hardware-software interface, incorporated in the Instruction set architecture (ISA), is arguably the most crucial interface in the computer system. An open ISA standard can help in increasing the innovation in ...

    • Design and implementation of a low power superscalar processor 

      Ravali, K. V. N. N. (Dhirubhai Ambani Institute of Information and Communication Technology, 2018)
      Designed and Implemented a Superscalar processor, where it fetches and issues two instructions simultaneously and it has 6 stages. Initially, concentrated on designing the architecture to make the processor executing ...

    • Design and Implementation of AI Accelerator based Coprocessor for IoT node using RISC-V ISA 

      Laddha, Prashant (2021)
      Semiconductor industry has seen a considerable amount of growth in the processor industry. The design of a processor is focused on two aspects namely power and performance. Hardware acceleration is an efficient method to ...

    • Design and implementation of low power processor design using RISC-V ISA 

      Ahuja, Priya (Dhirubhai Ambani Institute of Information and Communication Technology, 2019)
      This thesis, represents a design in which the processor is made to work once or twice on occurrence of external signal, therefore the processor remains idle most of the time. Unlike the processor used in mobile phones, ...

    • Design and Implementation of Low Power RISC V ISA based Processor and Coprocessor design for Matrix Multiplication 

      Gaurav, Tanya (2021)
      RISC V is an open-source ISA that is used to design the processor and the coprocessor architecture. For fulfilling the requirement of matrix multiplication, a low power and high-performance multiply and accumulate unit has ...

    • Design and implementation of low power superscalar processor 

      Thanki, Jigar (Dhirubhai Ambani Institute of Information and Communication Technology, 2018)
      As the Reduced Instruction Set Computing (RISC) philosophy architecture provides higher operating frequency and low power design as compared to Complex Instruction Set Computing (CISC) philosophy, a single core superscalar ...

    • Design and implementation of low power superscalar processor 

      Gupta, Shubhangi (Dhirubhai Ambani Institute of Information and Communication Technology, 2018)
      This thesis presents design of a low power, general purpose, 4 issue superscalar processor, which fetches 4 instructions simultaneously and executes them parallelly. The processor fetches the instruction in program order, ...

    • Design and implementation of low power superscalar processor 

      Kriti (Dhirubhai Ambani Institute of Information and Communication Technology, 2018)
      The processor architecture designed here is a modest step forward towards the designing of a power optimized superscalar processor. The heavy popularity of data intensive applications nowadays is demanding for high performance ...

    • Design and implementation power interrupt-driven processor using RISC-V ISA 

      Singh, Pranav (Dhirubhai Ambani Institute of Information and Communication Technology, 2019)
      From the past mistakes of popular ISA's and with the motivation to work on one of the most important abstraction layer, the RISC-V ISA steps forth to upend the status quo. Working towards a low power processor that entertains ...

    • Design of a Real Time Low Power Interrupt Driven Processor With Fair Scheduling 

      Shrotriya, Tushin (Dhirubhai Ambani Institute of Information and Communication Technology, 2017)
      "Recent times have seen a considerable amount of growth in the processor industry. The design of a processor is mainly focussed on two aspects namely, high performance or low power. While some high-end applications require ...

    • Design of AHB-Wishbone bridge 

      Mistry, Shailesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2004)
      System-on-Chip (SoC) design is performed through integration of pre-designed components, called intellectual Property (IP). Design reuse is a critical feature in SoC design. Design reuse is the simple concept of using IP ...

    • Design of an interrupt driven processor having deterministic exception response 

      Parikh, Sagar (Dhirubhai Ambani Institute of Information and Communication Technology, 2016)
      In recent times, we have seen an impressive growth of portable devices, audiovideobased multimedia products and wireless communication systems. To meetthe intensive computational requirements and complex real time functions, ...

    • Design of CMOS front end for 900MHz RF receiver 

      Harshey, Jitendra Prabhakar (Dhirubhai Ambani Institute of Information and Communication Technology, 2004)
      Portable wireless personal communication systems such as cellular phones, message pagers, and wireless modems traditionally have been built from a mixture of IC technologies. In fact if we section a commercial cellular ...

    • Design of frequency synthesizable delay locked loop 

      Shah, Hardik K. (Dhirubhai Ambani Institute of Information and Communication Technology, 2004)
      As the speed performance of VLSI systems increases rapidly, more emphasis is placed on suppressing skew and jitter in the clocks. Phase-locked loops (PLLs) and delay-locked loops (DLLs) have been typically employed in ...

    • Design of low power interrupt driven RISC-V instruction set processor for embedded systems 

      Patel, Ketul (Dhirubhai Ambani Institute of Information and Communication Technology, 2019)
      This thesis presents a design for low power, interrupt driven processor compatible with RISC-V Instruction Set Architecture (ISA). The processor is designed to target the application of home automation systems. To accomplish ...